1. Field of the Invention
The present invention relates to an analog/digital (referred to as A/D in the present specification) conversion circuit and a solid-state image pickup device having the A/D conversion circuit that convert an input analog voltage signal to a binary digital signal.
2. Description of the Related Art
Conventionally, in digital cameras, digital video cameras, endoscopes, and the like, a photoelectric conversion device that converts the incident light to an electrical signal is used. With advances in compactness and energy efficiency in digital cameras, video cameras, endoscope, and the like, photoelectric conversion devices are required to be compact and energy efficient. As an approach to achieving compact and energy-efficient photoelectric conversion devices, a photoelectric conversion device incorporating an A/D converter implemented with digital circuitry has been proposed (refer to, for example, Japanese Unexamined Patent Application, First Publication No. 2006-287879).
FIG. 17 shows the general constitution of a photoelectric conversion device in accordance with the related art. The photoelectric conversion device shown in FIG. 17 has a plurality of array blocks (sub-arrays) B1, B2, . . . (in FIG. 17 four rows by five columns) that have pixel blocks 90 with a two-dimensional array-like arrangement of pixels having photoelectric conversion elements that output pixel signals in response to the amount of incident light and A/D converters 91 that analog-to-digital convert the pixel signals output from the pixels of the pixel blocks 90.
FIG. 18 shows an example of the circuit configuration of the A/D converter 91 provided in each of the array blocks (sub-arrays) of FIG. 17. In the A/D converter 91 shown in FIG. 18, a plurality of delay units formed by various gate circuits (for example, a NAND gate and a plurality of inverter gates or plurality of buffer circuits) are connected in a ring configuration. In each delay unit within a delay circuit 911 the input signal (voltage) to be analog-to-digital converted is supplied, as the drive voltage of the delay units. Each delay unit within the delay circuit 911 is also supplied with a reference voltage.
In the A/D converter 91 shown in FIG. 18, for example, with the reference voltage of the delay circuit 911 as ground, when a high-level signal is input as the input pulse signal φPL, the input pulse signal φPL passes successively through each delay unit with a delay time responsive to the voltage difference between the input signal and the reference signal (ground), and circulates through the delay circuit 911. When the input pulse signal φPL is made the low level, the input pulse signal φPL stops circulating through the delay circuit 911.
When the input pulse signal φPL is circulating through the delay circuit 911, the number of stages of delay unit that the input pulse signal φPL passes through in a prescribed amount of time is established by the delay time of the delay unit, that is, the voltage difference between the input signal and the reference voltage (ground). A latch circuit 9121 latches signals output from the delay units within the delay circuit 911. An encoder circuit 9122, based on the signals held in the latch circuit 9121, detects the number of stages of delay units that the pulse signal φPL has passed through.
A counter circuit 9120 counts the number of times the input pulse signal φPL circulates within the delay circuit 911. An adder 9123 takes the value output from the counter circuit 9120 as the upper-order bit data (for example, a bits) and takes the value output from the encoder circuit 9122 as the lower-order bit data (for example, b bits) and outputs the digital data of a+b bits. The output value of the adder 9123 is the digital value after analog-to-digital conversion in accordance with the voltage of the input signal. In the photoelectric conversion device shown in FIG. 17, by taking the pixel signals output from the pixel blocks 90 the input signals as the input signal of the A/D converter 91, a digital value responsive to the amount of incident light is output.
In the conventional art, although there is no description of the specific circuit constitution regarding the encoder circuit 9122 shown in FIG. 18, it can be thought of as a combinatorial circuit in which circuits are provided for the number bits in accordance with the number of signals held by the latch circuit 9121 (that is, the number of delay units within the delay circuit 911) and that performs encoding by making the value of each of the bits either 0 or 1, in accordance with the logical state of the signals held by the latch circuit 9121. For this reason, it is necessary to provide a number of input circuits in the encoder circuit 9122 that is the same as the number of signals held by the latch circuit 9121. In this type of circuit configuration, however, the circuit scale of the encoder circuit 9122 grows and the size of the A/D converter 91 could become large.